Tiêu đề Advanced Computer Archi Reviewer ✅

IDENTIFICATION ❖ Pipelining ➢ A process of arrangement of hardware elements of the CPU such that its overall performance is increased. ❖ Stage 1 (Instruction Fetch) ➢ In this stage the CPU reads instructions from the address in the memory whose value is present in the program counter. ❖ Stage 2 (Instruction Decode) ➢ In this stage, instruction is decoded and the register file is accessed to get the values from the registers used in the instruction. ❖ Stage 3 (Instruction Execute) ➢ In this stage, ALU operations are performed. ❖ Stage 4 (Memory Access) ➢ In this stage, memory operands are read and written from/to the memory that is present in the instruction. ❖ Stage 5 (Write Back) ➢ In this stage, computed/fetched value is written back to the register present in the instructions. ❖ The cycles per instruction (CPI) value of an ideal pipelined processor is 1. ❖ Stall ➢ A cycle in the pipeline without new input. ❖ Structural dependency ➢ This dependency arises due to the resource conflict in the pipeline. ❖ Resource conflict ➢ A situation when more than one instruction tries to access the same resource in the same cycle. ❖ To minimize structural dependency stalls in the pipeline, we use a hardware mechanism called Renaming. ➢ According to renaming, we divide the memory into two independent modules used to store the instruction and data separately called Code memory(CM) and Data memory(DM) respectively. CM will contain all the instructions and DM will contain all the operands that are required for the instructions. ❖ Control Dependency (Branch Hazards)
➢ This type of dependency occurs during the transfer of control instructions such as BRANCH, CALL, JMP, etc. ❖ Branch Prediction ➢ The method through which stalls due to control dependency can be eliminated. ❖ Branch Penalty ➢ The number of stalls introduced duri.ng the branch operations in the pipelined processor. ❖ Total number of stalls introduced in the pipeline due to branch instructions = Branch frequency * Branch Penalty ❖ Flow dependency ➢ Also known as a data dependency or true dependency or read-after-write (RAW), occurs when an instruction depends on the result of a previous instruction. ❖ Anti-dependency ➢ Also known as write-after-read (WAR), occurs when an instruction requires a value that is later updated. ❖ Output dependency ➢ Also known as write-after-write (WAW), occurs when the ordering of instructions will affect the final output value of a variable. ❖ Operand Forwarding ➢ In operand forwarding, we use the interface registers present between the stages to hold intermediate output so that dependent instruction can access new value from the interface register directly. ❖ Control dependency ➢ Control dependencies are essentially the dominance frontier in the reverse graph of the control flow graph (CFG). ❖ Data Hazards ➢ Data hazards occur when instructions that exhibit data dependence, modify data in different stages of a pipeline. ❖ Uniform delay pipeline ➢ In this type of pipeline, all the stages will take the same time to complete an operation. ❖ Non-Uniform delay pipeline ➢ In this type of pipeline, different stages take different time to complete an operation.