Title Industrial Electronics-2020_S1.pdf ✅

Page 1 of 5 University of Moratuwa Faculty of Engineering Department of Electrical Engineering MSc/PG Diploma in Industrial Automation Semester 1 Examination 2020 EE5215 Industrial Electronics Time allowed: Two Hours ONLY September 2020 INSTRUCTION TO CANDIDATES: This paper contains 4 questions on 5 pages. Answer all questions. This paper accounts for 80% of the module assessment. The total maximum mark attainable is 100. The marks assigned for each question and sections thereof are indicated in square brackets. Only printed lecture notes are allowed. Assume reasonable values for any data not given in or with the examination paper. Clearly state such assumptions made on the script. If you have any doubt as to the interpretation of wording of question, make your own decision, but clearly state it in the script. All Examinations are conducted under the rules and regulations of the University.

Page 3 of 5 Question 1 (a) Using the datasheet for the SNx400, SNx4LS00, and SNx4S00 Quadruple 2-Input Positive-NAND Gates provided, Appendix 01, answer the following questions. i) How many gates can be driven by a single SN7400 NAND gate? ii) What are the noise margins of the SN7400? iii) Compute the average propagation delay for the SN7400 in the worst case. iv) Compute the power-delay product of the SN7400 in the worst case. [10 marks] (b) In a microcomputer, the microprocessor unit (MPU) is always communicating with one of the following: (1) random-access memory (RAM), which stores programs and data that can be readily changed; (2) read only memory (ROM), which stores programs and data that never change; and (3) external input/output (I/O) devices such as keyboards, video displays, printers, and disk drives. As it is executing a program, the MPU will generate an address code that selects which type of device (RAM, ROM, or I/O) it wants to communicate with. Figure shows a typical arrangement where the MPU outputs an eight- bit address code A15 through A8. The address code is applied to a logic circuit that uses it to generate the device select signals: RAM, ROM, and I/O. Analyze this circuit and determine the following. i) The range of addresses A15 through A8 that will activate ii) The range of addresses that activate iii) The range of addresses that activate Express the addresses in binary and hexadecimal format. [15 marks]
Page 4 of 5 Question 2 (a) For each statement indicate what type of FF is being described. i) Has a SET and a CLEAR input but does not have a CLK input ii) Will toggle on each CLK pulse when its control inputs are both HIGH iii) Has an ENABLE input instead of a CLK input iv) Is used to transfer data easily from one FF register to another v) Has only one control input vi) Has two outputs that are complements of each other vii) Can change states only on the active transition of CLK viii) Is used in binary counters [10 marks] (b) Refer to the counter circuit in Figure Q2.1. Assume that all asynchronous inputs are connected to When tested, the circuit waveforms appear as shown in Figure Q2.2. Consider the following list of possible faults. For each one, indicate “yes” or “no” as to whether it could cause the observed results. Explain each response. i) CLR input of is open. ii) output’s transition times are too long, possibly due to loading. iii) output is shorted to ground. iv) hold time requirement is not being met. [15 marks] Figure Q2.1: The counter circuit Figure Q2.2: The circuit waveforms