Title simulations (interview prep session 27 part 1).pdf ✅

SIMULATION
SIMULATION To validate the patterns that were generated during ATPG.

If the same patterns is given to the tester, our patterns will fail on the tester. Since it can’t apply a value on an internal pseudo port. So we need to do simulation. If we have used internal cut-points, simulations will also fail. Because simulation tool also can’t apply a value on an internal pseudo port. At the time of simulation, rsta_reg/QB is controlling the reset of the flop. So reset of the flops are toggling. So it will fail.