Title ATPG (part 1) typed.pdf ✅

+91-9986194191 | www.vlsiguru.com | www.inskill.in FAULT SIMULATION: • During ATPG, the design (EDT inserted netlist) is provided to the ATPG tool. The ATPG tool keeps this design (good machine) and creates another design by inducing all possible faults into it (faulty machine). • The tool generates patterns for good machine and keeps that as expected response (good value). • Then the tool applies patterns for faulty machine and tries to see whether the pattern detects the fault. • If good value is not the same as faulty value the fault is detected and vice versa. • Based on the result of fault simulation, the tool categorizes the faults into various classes. The optimized set of patterns which are obtained during ATPG will be given to the tester for testing the chip after manufacturing. (Not detected)