Title Verilog codes.pdf ✅

Dataflow Modeling //OR gate, NAND gate, NOR gate, XOR gate Module gates( Input a, Input b, Output y, Output x, Output z, Output w, ); Assign y=a|b; Assign x=~(a&b); Assign w=~( a|b); Assign z=a^b; Endmodule //Half adder Module halfadder( Input a, Input b, Output s, Output c, ); Assign s=a^b; Assign c=a&b;
endmodule //Full Adder Module fulladder( Input a, Input b, Input ci, Output s, Output co, ); Assign s= a^b^ci; Assign co=(a&b)|(b&ci) |(ci&a); Endmodule //2:1 mux Module 21mux( Input s; Input a; Input b; Output z, ); Assign z=((~s)&a) |(s&b) ; Endmodule //4 bit Carry look ahead adder module 4bitclaaddr(
output [3:0]s, output cout,PG,GG, input [3:0]a,b, input cin ); Wire[3:0]G,P,C; Assign G=a&b; Assign P=a^b; Assign C[0]=cin; Assign C[1]=G[0] |(P[0]&C[0]); Assign C[2]=G[1] |(P[1]&G[0])|(P[1]&P[0]&C[0]); Assign C[3]=G[2] |(P[2]&G[1])|(P[2]&P[1]&G[0]) | (P[2]&P[1]&P[0]&C[0]); Assign cout=G[3] |(P[3]&G[2])|(P[3]&P[2]&G[1]) | (P[3]&P[2]&P[1]&G[0]) | (P[3]&P[2]&P[1]&P[0]&C[0]); Assign s=P^C; Assign PG= P[3]&P[2]&P[1]&P[0]; Assign GG= G[3] |(P[3]&G[2])|(P[3]&P[2]&G[1]) | (P[3]&P[2]&P[1]&G[0]); Endmodule //Encoder 8:3 module encoder83df(din, a, b, c); input [0:7] din; output a; output b; output c; assign a=din[4] | din[5] | din[6] | din[7];
assign b=din[2] | din[3] | din[6] | din[7]; assign c=din[2] | din[4] | din[6] | din[7]; endmodule //4:1 mux module mux41data (din,s,y); input [0:3] din; input[0:1]s; output out; assign out=din[s]; endmodule Behavioral modeling //2:1 mux using if else module mux2x1_bh(A,B,select,OUT); input A,B,select; output reg OUT; always @ (select or A or B) if (select == 1) OUT = A; else