Title IIT-JAM DIGITAL ELECTRONICS_ASSIGNMENT.pdf ✅

1 North Delhi : 56-58, First Floor, Mall Road, G.T.B. Nagar (Near Metro Gate No. 3), Delhi-09, Ph: 011-41420035 South Delhi : 28-A/11, Jia Sarai, Near-IIT Metro Station, New Delhi-16, Ph : 011-26851008, 26861009 IIT-JAM PHYSICS 2024 SECTION : ELECTRONICS PRACTICE SET : DIGITAL ELECTRONICS 1. 4-bit 2’s complement representation of a decimal number is 1000. The number is (a) 8 (b) 0 (c) –7 (d) –8 2. Considering positive logic, a digital circuit implements the function (f) shown below. f 1 Considering negative logic the function (f 2 ) implemented by the digital circuit is (a) f2 (b) f2 (c) f2 (d)All of these 3. The logic evaluated by the circuit at the output is Output X Y (a) XY YX  (b) ( ) X Y XY  (c) XY XY  (d) XY XY X Y    4. In the digital circuit given below, F is Z X Y F (a) XY YZ  (b) X XZ  (c) XY YZ  (d) XZ Y 5. A particular number system has 18 symbols from 0 to 9, A, B, C, D, E, F, G and T. If two numbers GATE and ECE are given to an adder then output of the adder is (a) G7CA (b) T76C (c) T7CA (d) G76A 6. Match the logic gates in Column-A with their equivalents in Column-B. Column-A Column-B P. 1. Q. 2.
2 North Delhi : 56-58, First Floor, Mall Road, G.T.B. Nagar (Near Metro Gate No. 3), Delhi-09, Ph: 011-41420035 South Delhi : 28-A/11, Jia Sarai, Near-IIT Metro Station, New Delhi-16, Ph : 011-26851008, 26861009 R. 3. S. 4. Codes: P Q R S (a) 2 4 1 3 (b) 4 2 1 3 (c) 2 4 3 1 (d) 4 2 3 1 7. Which one of the following circuits is the minimized logic circuit for the circuit shown in the figure below ? A C B (a) (b) (c) (d) 8. The Boolean expression ( ) ( ) a b c d b c      simplifies to (a) 1 (b) a b. (c) a b. (d) 0 9. A and B are the logical inputs and X is the logical output shown in the figure. The output X is related to A and B by X A B (a) X AB BA   (b) X AB BA   (c) X AB AB   (d) X AB BA   10. Four digital outputs V, P, T and H monitor the speed v, type pressure p, temperature t and relative humidity h of a car. These outputs switch from 0 to 1 when the values of the parameters exceed 85 km/hr, 2 bar, 40oC and 50%, respectively. A logic circuit that is used to switch ON a lamp at the output E is shown below E V P T H Which of the following conditions will switch the lamp ON? (a) v < 85 km/hr, p < 2bar, t > 40oC, h > 50% (b) v < 85 km/hr, p < 2bar, t > 40oC, h < 50% (c) v > 85 km/hr, p < 2bar, t > 40oC, h < 50% (d) v > 85 km/hr, p < 2bar, t < 40oC, h > 50%
3 North Delhi : 56-58, First Floor, Mall Road, G.T.B. Nagar (Near Metro Gate No. 3), Delhi-09, Ph: 011-41420035 South Delhi : 28-A/11, Jia Sarai, Near-IIT Metro Station, New Delhi-16, Ph : 011-26851008, 26861009 11. For the logic circuit shown in the figure below A B C X a simplified equivalent circuit is (a) A B C X (b) X A B C (c) X A B C (d) X A B C 12. The logic circuit shown in the figure below HIGH Y A B implements the Boolean expression (a) Y A B  . (b) Y A B  . (c) Y A B  . (d) Y A B   13. Consider the digital circuit shown below in which the input C is always high (I) Z A B C (HIGH) The truth table for the circuit can be written as 0 0 0 1 1 0 1 1 A B Z The entries in the Z column (vertically) are (a) 1010 (b) 0100 (c) 1111 (d) 1011 14. Consider the below statements, which of the following options is TRUE. (a) Two input NAND gate obeys associative law (b) Two input EXNOR gate obeys associative law (c) Two input NOR gate obeys associative law (d) Two input EXOR gate does not obeys commutative law
4 North Delhi : 56-58, First Floor, Mall Road, G.T.B. Nagar (Near Metro Gate No. 3), Delhi-09, Ph: 011-41420035 South Delhi : 28-A/11, Jia Sarai, Near-IIT Metro Station, New Delhi-16, Ph : 011-26851008, 26861009 15. Which of following is valid (a) ab ab ab ab    (b) ab ab b ab    (c) XOR + 2NOT = XNOR (d)XNOR + 2NOT = XOR 16. The 2’s complement representation of –17 is (a) 101110 (b) 101111 (c) 111110 (d) 110001 17. In a particular number system having base B. 10 ( 41) 5 B  . The value of ‘B’ is _________ 18. The Boolean function Y = AB + CD is to be realized using only 2-input NAND gates. The minimum number of gates required is (a) 2 (b) 3 (c) 4 (d) 5 19. For the circuit shown in Fig. the boolean expression for the output Y in terms of inputs, P, Q, R and S is P Q R S Y (a) P Q R S    (b) P Q R S    (c) P Q R S     (d) P Q R S     20. The Boolean function x y xy x y      is equivalent to (a) x y    (b) x + y (c) x y   (d) x y  21. What is the minimum number of NAND gates required to implement a 2-input EXCLUSIVE OR fucntion without using any other logic gate? (a) 3 (b) 4 (c) 5 (d) 6 22. What is the boolean expression for the output f of the combinational logic circuit of NOR gates given below? P Q Q R P R Q R F (a) Q R (b) P Q (c) P R (d) P Q R   23. Transform the following logic circuit (without expressing its switching function) into an equivalent logic circuit that employs only NAND gates each with 2-inputs. (a) 4 (b) 5 (c) 6 (d) 7