Title 2023 Apr-May Digital Electronic Logic Design.pdf ✅

Printed Pages-4 Roll No. :. B022314(022) (AICTE Scheme) (CSE Engg. Branch) B. Tech. (Third Semester) Examination, April-May 2023 Time Allowed : Three hours Maximum Marks: 100 Minimum Pass Murks : 35 DIGITAL ELECTRONICS & LOGIC DESIGN TTUTE Unit-I RAPUR using NAND gates only. LIBRARY Note : Part (a) is compulsory from each unit and carry equal 4 marks. attempt any two parts from (b), (c) and (d) from each question and carry equal 8 marks. B0223 14(022) RAIPAIR. C.G.) 1. (a) Convert the Boolcan Expression (4+ B)C)D OF TEC PTO 49010
(b) Reduce the following function using Karnaugh map and implement using basic gates j(A, B.C D)= ABD + ABCD+ ABD+ ABCD (c) Reduce the following equation using Quine Meclusky method of minimisation F(4, B.C, D)= Em(0. 1, 3, 4, 5, 7, 10, 13, 14, 15) (d) Do as directed |2 | () Convert (2AC5-D), to decimal, octal and binary () Solve ( DDCC),, + (BBAA) =(:.. () Noise margin 2. (a) Define the following parameter. (ü) Power dissipation Unit-II (Hüi) Propogation delay (iv) Fan out Cutpt (b) Draw the circuit diagram and explain the operation of 2-input TTL NAND gate with open collector B022314(022) (c) Explain with neat diagram interfacing of a TTL gate driving CMOS gate and Vice versa (d) Write short note on : () PLA | 3 | (iü) PAL and FPGA Unit-iI 3. (a) Explain design procedure for combinational circuit. (b) Draw and explain the block diagram of n-bit parallel adder circuit. (c) Design 32 to l multiplexer using two 74LSI50 ICs (d) Draw and explain circuit for 3 to 8 decoder Unit-IV 4. (a) What is race around condition? How it is avoided (b) Explain the working of 4 bit asynchronous counter (c) What are registers Differentiate betvween Buffer Register & shift register BO22314(022) 4 4 PTO
{d} Design the counter that goes through state 1. 2, 4, 5. 7. 10, I, |4 5. (a) Definc finite stale machine. machine 1050} tIsing J-K flip lops. (b) Dilcrent iate bet wecn Mcaly machine and Moore Unit-V structural description. (c) What is VHDL. Give data flow and algorithmic and (d) Write VHDL code to design 4 to l MUX. B022314(022)