Title Basics of Analog Flow A Design-Oriented Approach.pdf ✅

Basics of Analog Flow: A Design- Oriented Approach Rapid Adoption Kit (RAK) Product Version: Virtuoso ICADVM20.1 ISR30, Spectre 21.1 ISR16, PEGASUS 22.20, Quantus 22.1.0-p089 June 2024
Learn more at Cadence Learning and Support Portal - https://support.cadence.com © 2024 Cadence Design Systems, Inc. DO NOT DISTRIBUTE. Page 2 Copyright Statement © 2024 Cadence Design Systems, Inc. Cadence and the Cadence logo are registered trademarks of Cadence Design Systems, Inc. All others are the property of their respective holders. This content is Cadence Confidential and for Cadence customers only. DO NOT DISTRIBUTE.
Basics of Analog Flow: RAK Learn more at Cadence Learning and Support Portal - https://support.cadence.com © 2024 Cadence Design Systems, Inc. DO NOT DISTRIBUTE. Page 3 Contents Purpose..........................................................................................................................4 Audience........................................................................................................................4 Terms.............................................................................................................................4 Overview........................................................................................................................5 Module 1: Initial Setup ...................................................................................................6 Generating a cds.lib File for Virtuoso......................................................... 6 Creating a New Library and Cell.............................................................. 13 Module 2: Schematic Design.......................................................................................17 Schematic Creation Using Virtuoso Schematic Editor ............................ 17 Symbol Creation ...................................................................................... 24 Module 3: Schematic Testbench .................................................................................29 Testbench Creation.................................................................................. 29 Modifying DUT Parameters...................................................................... 41 Module 4: Pre-Layout Simulation ................................................................................45 Simulation Setup Using ADE Explorer and Assembler ........................... 45 Waveform Results Analysis ..................................................................... 60 Generating Expressions........................................................................... 74 Design Tuning Using Parameters............................................................ 82 Backannotation of Tuned Parameters ..................................................... 93 Module 5: Layout .........................................................................................................95 Layout XL................................................................................................. 95 Transistor Abutment............................................................................... 100 Placement .............................................................................................. 106 Routing................................................................................................... 115 DRC Tests.............................................................................................. 128 LVS (Layout Versus Schematic)............................................................ 135 Module 6: Post-Layout Simulation.............................................................................141 Using Quantus to Create a DSPF File................................................... 141 Using Quantus to Create a Smart View................................................. 143 Creating a Config View Using Virtuoso Hierarchy Editor ...................... 146 Post-Layout Simulations on ADE Assembler ........................................ 151 Support ......................................................................................................................157 Feedback ...................................................................................................................157
Basics of Analog Flow: RAK Learn more at Cadence Learning and Support Portal - https://support.cadence.com © 2024 Cadence Design Systems, Inc. DO NOT DISTRIBUTE. Page 4 Purpose This RAK introduces the steps of creating an analog design from initial requirements to the sign-off stage. Audience This RAK is intended for designers who are new to Virtuoso or those who would like an overview of the complete custom flow using the latest Cadence tools. For this RAK, you do not require prior knowledge of Cadence tools. Terms ADE Analog Design Environment LMB Left Mouse Button CIW Command Interpreter Window